1. Field of Invention
This invention relates generally to memory arrays and specifically to timing sequences for DRAM arrays.
2. Description of Related Art
Developed as a less expensive alternative to Static RAM (SRAM), dynamic RAM (DRAM) is presently used as the main memory of most computer systems and accounts for nearly 70% of the global semiconductor memory market. Since DRAM is much slower than SRAM, the cost savings realized by employing DRAM as main memory must be balanced with the slower speeds of DRAM. In particular, it is desirable to minimize the speed mismatch between the microprocessor and the main memory of a computer system. Otherwise, the effective rate at which the microprocessor processes information is undesirably limited by the speed of main memory, i.e., DRAM.
In order to improve this speed mismatch between the microprocessor and main memory, most computer systems include a small SRAM cache memory between the microprocessor and main memory. The cache memory stores information most frequently used by the microprocessor. When information requested by the microprocessor is stored within cache memory, the information is quickly retrieved without having to access main memory. In this manner, latency delays associated with DRAM may be hidden, thereby increasing the data rate with which the microprocessor processes information.
Presently, microprocessor speeds are increasing at a much faster rate than are DRAM speeds. Indeed, while today's microprocessors can operate at speeds exceeding 666 MHZ, DRAM speeds remain below 100 Mhz. While the use of cache memory increases the data rate of an associated microprocessor, cache memory size is limited by the high cost of SRAM. Accordingly, merely increasing the size of cache memory to compensate for the widening speed mismatch between microprocessors and DRAM is not commercially feasible. Therefore, there is a ever-increasing need to improve the speed of DRAM.
A conventional DRAM includes one or more arrays of cells arranged in columns and rows. Externally generated addresses specifying the location of a cell desired to be read from or written to are provided to the DRAM via input address lines. To read the contents of a selected cell in a DRAM array, the row address of the selected cell is clocked into a row address buffer on the falling edge of a row address strobe RAS signal. The contents of all cells within the row specified by the row address are latched into a bank of associated sense amplifiers. The column address of the selected cell is then clocked into a column address buffer on the falling edge of a column address strobe CAS signal. The column address selects a sense amplifier that corresponds to the selected cell. In response thereto, the contents of the selected sense amplifier is forwarded to an output buffer, thereby allowing the binary state of the selected cell to be read.
Data is written to DRAM in a similar manner. To write data to a selected cell, the row address is clocked on the falling edge of the RAS signal, thereby loading the contents of a selected row of cells into associated sense amplifiers. Data is then provided to an input buffer via associated input pins. The column address of the selected cell is clocked on the falling edge of the CAS signal. Data held within the input buffer is then latched into the sense amplifiers which correspond to the cell or cells selected for writing. The contents of the sense amplifiers are then written into the corresponding row of cells during a refresh operation.
The most commonly used DRAM is the extended data out (EDO) DRAM. Referring now to FIG. 1, a x16 EDO DRAM 10 includes sixteen arrays 12 each containing memory cells arranged in 512 rows by 512 columns. Each array 12 has associated therewith a row decoder 14 and an I/O gating circuit 16. Each row decoder 14 is coupled to the 512 rows of an associated array 12 via word lines 18. Each gating circuit 16 includes 512 sense amplifiers coupled to respective columns of an associated array 12 via bit lines 20. Each gating circuit 16 is coupled to an associated one of column decoders 22 via lines 24. An input buffer 26 stores data to be written into selected cells of the arrays 12, and an output buffer 28 stores data read from selected cells of the arrays 12. A refresh controller 32 and a refresh counter 34 periodically refresh data stored within the memory cells of the DRAM 10 in a well known manner. A row address strobe buffer 36 provides the RAS signal to the row address buffers 38, to the column address buffers 40, and to the refresh controller 32. A column address strobe buffer 42 provides the CAS signal to the column address buffers 40, to the refresh controller 32, to the input buffer 26, and to the output buffer 28. A control buffer 44 provides write enable (WE) and output enable (OE) signals to the input buffer 26 and to the output buffer 28. Signals WE and OE select the DRAM 10 for writing operations and read operations, respectively.
A cell selected for reading is addressed using 18 externally generated address bits received on the input address pins A0-A8, as follows. Referring also to the timing diagram of FIG. 2, the first 9 bits of the address, which constitute the row address of the selected cell, are held on the input pins A0-A8 until the row address stabilizes, i.e., become valid, as indicated by .tau..sub.ASR. The RAS signal goes low and latches the row address bits held on the input pins A0-A8 into the row address buffers 38, as indicated by ROW ADDR (1) in FIG. 2. The row address bits are held on the input pins A0-A8 until the RAS signal stabilizes, as indicated by .tau..sub.RAH. The row address then is provided to row decoders 14 which, in turn, select one of word lines 18. The contents of the cells associated with the selected word line 18 are forwarded into corresponding sense amplifiers of the gating circuits 16 via the bit lines 20.
The next 9 bits of the address, which constitute the column address of the selected cell, are provided to the input pins A0-A8 and held until valid, as indicated by .tau..sub.ASC. The CAS signal goes low and latches the column address bits into the column address buffers 40, as indicated by COL ADDR (1) in FIG. 2. The time lapsed between the time at which the row address becomes valid and the time at which the column address become valid is called the RAS to CAS signal delay and is given by .tau..sub.RCD. The column address bits are held on the input pins A0-A8 until the CAS signal stabilizes, as indicated by .tau..sub.CAH. The column address bits are then provided to the column decoder 18 which, in response thereto, selects the sense amplifier of the gating circuits 16 which corresponds to the selected cell.
The data stored within the selected sense amplifier is provided to the output buffer 28 and thereafter appears as output data on the output pins DQ0:15!, as indicated by DATA-OUT(1) in FIG. 2. The time lapsed between the latching of the column address and the corresponding data appearing on the output pins DQ0:15! is called the access time from the CAS signal, as indicated by .tau..sub.CAC, the time lapsed between the latching of the row address and the corresponding data appearing on the output pins DQ0:15! is called the access time from the RAS signal, as indicated by .tau..sub.RAC, and the time lapsed between the column address appearing on the input pins A0-A8 and the corresponding data appearing on the output pins DQ0:15! is called the access time from the column address, as indicated by .tau..sub.AA.
After data from the selected cell is read, the CAS signal goes high, as shown in FIG. 2. A second externally generated 9-bit column address is provided to pins A0-A8 and allowed to stabilize, as indicated by .tau..sub.ASC. The next falling edge of the CAS signal latches the second column address into the column address buffers 40, as indicated by COL ADDR (2) in FIG. 2. The time lapsed between falling edges of the CAS signal is called the CAS signal cycle time, as indicated by .tau..sub.PC. Data corresponding to the second column address appears on the output pins DQ0:15! a time I.sub.CAC after the second falling edge of the CAS signal, as indicated by DATA-OUT (2).
This process continues until each cell within the row of cells selected by the first row address has been read. A new row address may then be provided to the input pins A0-A8 on the next falling edge of the RAS signal, thereby selecting a new row of cells to be read. Cycling the CAS signal while holding the RAS signal low allows the bits of a selected row of memory to be randomly accessed without having to latch a new row address. In this manner, only one row address set-up and hold time is required to read an entire row of data from the arrays 12.
Data is written to selected cells of the DRAM 10 in a similar manner. The new data is provided on the I/O pins DQ0:15! and then latched into the data-in buffer 26 on the falling edge of the CAS signal. After the contents of the selected row are latched into corresponding sense amplifiers of the gating circuits 16, as described above, the falling edge of the CAS signal latches the first column address and, in response thereto, data stored within the data-in buffer 26 is clocked into the sense amplifier which corresponds to the selected cell. Second data is then latched into the input buffer 26 on the second falling edge of the CAS signal. The next falling edge of the CAS signal latches the second column address which, in turn, results in the second data being latched into the sense amplifier which corresponds to the cell selected by the second column address. This process continues until data within each of the sense amplifiers corresponding to the selected row has been replaced with data stored in the input buffer 26. Data within the sense amplifiers is written to the selected row of cells during a subsequent write operation.
The access speed of the DRAM 10 may be increased by including a burst counter 52, as illustrated by DRAM 50 in FIG. 3. The burst counter 52 has an input terminal coupled to receive a column address latched from the input pins A0-A8, and has an output terminal coupled to the column decoders 22. When the burst counter 52 is not enabled, the DRAM 50 operates in page mode, i.e., in a manner identical to the DRAM 10. When the burst counter 52 is enabled, DRAM 50 operates in burst mode, as follows. An externally generated row address is latched from the input pins A0-A8 on the falling edge of the RAS signal, as described above, and data from a row of cells is latched into associated sense amplifiers of the gating circuits 16.
On the falling edge of the CAS signal, an externally generated column address is latched from input pins A0-A8 into the column address buffers 40, as described above. The column address is forwarded to the burst counter 52 and to the column decoders 22. The burst counter 52 is initialized to the column address, and the column decoders 22 select one of the sense amplifiers within the gating circuits 16, thereby causing data stored within the cell selected by the first column address to appear on the output pins A0-A8, as indicated by DATA-OUT (1) in FIG. 4.
When the CAS signal goes high, the burst counter 52 increments one memory address location, thereby internally generating a second column address. On the next falling edge of the CAS signal, the burst counter 52 provides the second column address to the column decoders 22 which, in turn, cause data stored within the cell selected by the second column address to appear as output on the output pins DQ0:15!, as indicated by DATA-OUT (2) in FIG. 4. The burst counter 52 provides a third column address to column decoders 22 on the third falling edge of the CAS signal, and so on, until an entire row of data is read on the output pins DQ0:15!.
Thus, after the first column address is latched from input pins A0-A8, all subsequent column addresses are internally generated by the burst counter 52. Accordingly, the burst counter 52 allows an entire row of data to be accessed using a single set of externally generated row and column addresses and, therefore, eliminates the access time .tau..sub.AA for the second and all subsequent column addresses associated with a selected row. Thus, burst mode operation allows the second and all subsequent data of a selected row to be accessed at a much faster rate, as compared to the operation of the DRAM 10 (FIG. 1). However, since burst mode operation improves only the accessing speed of the second and subsequent data of a selected row, the access time .tau..sub.AA of the first column address remains and, as overall cycle time improves, begins to dominate the overall cycle time of DRAM. Moreover, burst mode operation does not allow data within a selected row to be randomly accessed. Thus, it would be advantageous to reduce or even eliminate the access time .tau..sub.AA of the first column address of a DRAM while preserving the ability to randomly access data within a selected row of memory.